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DAQ Trigger High Energy Physics

Session chair: Purschke , Martin L. (Brookhaven National Laboratory, Physics Department, Upton, USA); Mannel , Eric J. (Brookhaven National Laboratory, Physics Dept, Upton, USA)
Shortcut: N-17
Date: Wednesday, 20 October, 2021, 11:45 AM - 1:45 PM
Room: NSS - 1
Session type: NSS Session


Click on an contribution to preview the abstract content.

11:45 AM N-17-01

Demonstrator system for the high-luminosity upgrade of the ATLAS hadronic Tile Calorimeter electronics (#935)

J. Abdallah1

1 University of Texas, Department of Physics, Arlington, Texas, United States of America

On behalf of the ATLAS Tile Calorimeter collaboration


The ATLAS Tile Calorimeter (TileCal) is a hadronic sampling calorimeter made of steel tiles as absorber and plastic scintillating tiles as active medium. The scintillating tiles are read out by wavelength shifting fibers to photomultiplier tubes (PMTs). The analog PMT signals are shaped, conditioned, and then digitized every 25 ns before being sent off-detector. The high-luminosity upgrade to the LHC (HL-LHC) presents significant challenges for ATLAS and TileCal,  including greater radiation exposure to the on-detector electronics and increased pileup from low momentum collisions affecting trigger selection performance. A full replacement of the on- and off-detector electronics for TileCal will take   place in preparation for the HL-LHC program. in 2026. The new system is designed to digitize and transmit all sampled calorimeter data to the off-detector systems, where the data are stored in latency pipelines while quasi-projective digital trigger tower sums are formed and forwarded to the level-1 trigger. The design of the Phase-II system has included a long R&D program and extensive test beam studies. The design includes state of the art electronics with extensive use of redundancy and radiation tolerant electronic components to avoid single points of failure. Multi-Gbps optic links drive the high volume of data transmission and Field Programmable Gate Arrays (FPGAs) provide digital functionality both on- and off detector. A hybrid demonstrator prototype module, instrumented with new   module electronics as well as interfaces for backward compatibility with the present system was assembled and inserted in ATLAS in June 2019 in order to gain experience in actual detector conditions. We present the current status and test results from the Phase-II upgrade demonstrator module running in ATLAS.

Keywords: HL-LHC, ATLAS, TileCal, Upgrade, Electronics
12:00 PM N-17-02

Commissioning of the FASER Trigger and Data Acquisition prior to proton-proton collision data-taking at the LHC (#1053)

C. Antel1

1 University of Geneva, Particle Physics Department, Geneva, Genève, Switzerland

On behalf of the FASER Collaboration


FASER is a newly installed experiment at the LHC designed to search for long lived particles produced in high energy proton collisions and decaying several 100 meters downstream. As the experiment aims to measure a rare hypothetical process, it is crucial that the experiment’s trigger and data acquisition (TDAQ) system runs reliably and with minimal deadtime, quick to catch errors and raise alerts. The expected trigger rate is 500-1k Hz, dominated by energetic experimental background muons entering the front of the detector. The readout and hardware control is performed on both custom and commercial hardware, while data processing and event building is done in software. The FASER DAQ is envisioned to be a self-sustaining system during data-taking commencing next year, aiming to be live for the full LHC Run 3 luminosity. The full detector was installed in the tunnel in March 2021, and the readout system has since then been stress tested by collecting on the order of 100 million noise and cosmic-ray events. This talk will present the TDAQ system design, covering the design philosophy to execution. This will be followed by the measured performance of the system during commissioning, and the challenges encountered, in the context of full system runs over multiple days and high rate tests designed to push the system’s limits.

AcknowledgmentI wish to thank the Particle Physics Department of the University of Geneva for the support, allowing me to contribute to this research. In addition, the FASER collaboration is thankful for the financial support of CERN, the Heising Simons Foundation and the Simons Foundation, as well as the technical support of various departments at CERN.
Keywords: trigger, data acquisiiton, FASER, LHC
12:15 PM N-17-03

The Prototype Hardware Design and Test of Global Common Module for Global Trigger System of the ATLAS Phase II Upgrade (#274)

S. Tang1

1 Brookhaven National Laboratory (BNL), Upton, New York, United States of America

This is a submission on behalf of ATLAS TDAQ speakers committee. The presenter will be assigned later once we are notified this contribution is accepted.


The HL-LHC is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the LHC Runs 1-3 combined (up to 4000 fb−1 ). Meeting these requirements poses significant challenges to the hardware design of Trigger and Data Acquisition system. A baseline architecture, based on a single-level hardware trigger with a maximum rate of 1 MHz and 10 µs latency, is proposed for ATLAS.
The hardware-based Level-0 Trigger system is composed of the Level-0 Calorimeter Trigger (L0Calo), the Level-0 Muon Trigger (L0Muon), the Global Trigger and the Central Trigger sub-systems. The Global Trigger is a new subsystem, which will perform offline-like algorithms on full-granularity calorimeter data. The calorimeter detector subsystems, FEXs, and MUCTPI provide serial data for each bunch crossing to the MUX layer. These signals are then time-multiplexed and the signals for a given event are transported to a single GEP node that executes the algorithms. The results are then sent to the CTP through the CTP Interface.
The hardware implementation of the Global Trigger consists of three primary components: a Multiplexer Processor (MUX) layer, a GEP layer, and a demultiplexing Global-to-CTP Interface (CTP Interface), all of which have identical hardware composed of ATCA modules and FPGAs with many multi-gigabit transceivers. The single Global Common Module (GCM) hardware is implemented across the Global Trigger system, minimizing the complexity of the firmware and simplifying the system design and long-term maintenance.

Keywords: LHC, ATLAS, Global Trigger, GCM, FPGA
12:30 PM N-17-04

FELIX: the new ATLAS readout system for the High-Luminosity LHC era (#278)

W. Panduro Vazquez1, M. Gebyehu2, A. Pellegrino2

1 Royal Holloway, University of London, Egham, United Kingdom
2 NIKHEF, Amsterdam, Netherlands

This is a submission on behalf of ATLAS TDAQ speakers committee. The presenter will be assigned later once we are notified this contribution is accepted.


Over the next decade, the ATLAS experiment will be required to operate in an increasingly harsh collision environment. To maintain physics performance, the ATLAS experiment will undergo a series of upgrades during major shutdowns. A key goal of these upgrades is to improve the capacity and flexibility of the detector readout system. To this end, the Front-End Link eXchange (FELIX) system was developed as the new interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. FELIX functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. The serial links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. FELIX uses commodity server technology in combination with FPGA- based PCIe I/O cards. FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run a new multi-threaded software infrastructure for event fragment building, buffering and detector-specific processing to facilitate online selection. This presentation will cover the design of FELIX, as well as its planned evolution for High Luminosity LHC. The results of the installation and commissioning activities from spring 2021 will be presented, alongside those from ongoing High- Luminosity LHC demonstrator programmes.

Keywords: DAQ, GBT, Readout
12:45 PM N-17-05

Performance of the amplifier-shaper-discriminator ASICs produced for the ATLAS MDT chambers at the HL-LHC (#390)

S. Abovyan1, V. Danielyan1, A. Grasser1, O. Kortner1, H. Kroha1, R. Richter1, S. Simeonov1

1 Max-Planck-Institut für Physik, München, Bavaria, Germany


The front-end electronics of the ATLAS muon drift-tube chambers will be upgraded in the experiment's phase-II upgrade to comply with the new trigger and read-out scheme at the HL-LHC. A new amplifier shaper discriminator chip was developed in 130 nm Global Foundries technology for this upgrade. A preproduction of 7500 chips was launched in 2019 and tested in 2020. The presentation will summarize the functionality of the new ASD chip, the test set-up and testing procedure as well as the test results which show a production yield of 93%. Based on the successful test of the preproduction chip the serious production of 80,000 chips was carried out in fall 2020. The tests of a sample of 1000 production chips show the same yield as the preproduction chips.

AcknowledgmentWe would like to Dr. Chrysostomos Valderanis from Ludwig-Maximilians-University Munich for providing us with the chip tester and his introduction to the use of the tester.
Keywords: amplifier, shaper, drift tubes, HL-LHC, muon
1:00 PM N-17-06

The data acquisition system to test and characterize the pixel detector modules of the CMS inner tracker for the High Luminosity upgrade of LHC (#408)

M. E. Dinardo1

1 Università degli Studi di Milano Bicocca, Physics Department "G. Occhialini", Milano, Italy


The LHC will be upgraded to the High Luminosity LHC (HL-LHC) in the coming years to reach an instantaneous luminosity as high as 7.5x10^34 cm^-2 s^-1, hence increasing the discovery potential of the ATLAS and CMS experiments. To preserve physics object performance despite an average pile-up of 200, the CMS detector will be significantly upgraded. In this respect, the Inner Tracker envisages using smaller, x6, pixels with respect to the present detector, resulting in an unprecedented number of channels, about two billion. The Inner Tracker frontend chip features a data readout speed of 1.28 Gbps, and a downlink for clock, trigger, and commands of 160 Mbps. The communication between the frontend and the backend electronics occurs through an optical link base on a custom Low-power Gigabit Transceiver which sends data at 10 and 2.5 Gbps on the uplink and downlink, respectively. A dedicated data acquisition system, written in C++ and based on a custom micro Data, Trigger, and Control board, equipped with a Xilinx Kintex 7 FPGA, was developed to fully test and characterize the pixel modules. The system architecture and its capabilities are presented in this note.

Keywords: HL-LHC, CMS, DAQ, pixel, detector
1:15 PM N-17-07

Athena: a 192-Channel Analog Pulse Processing and Data Acquisition Platform (#553)

P. King1, 2, U. Corona1, M. Gugiatti1, 2, M. Carminati1, 2, C. Fiorini1, 2

1 Politecnico di Milano, DEIB, Milano, Italy
2 INFN, Sezione di Milano, Milano, Italy


The low-noise readout of large pixellated detectors, especially when the number grows into the hundreds, represents a challenge for both front-end and back-end electronics. The TRISTAN project for keV-scale sterile neutrino search is planning to install a 3486-pixel Silicon Drift Detector (SDD) matrix into KATRIN experiment spectrometer. The matrix will be divided into 21 modules of 166 monolithical SDDs each.
In this paper, we present Athena, a 192-channel Analog Pulse Processing and Data Acquisition platform that will be used for the characterisation of the TRISTAN detectors. The analog front-end operations are carried out by SFERA ASIC, that is tasked with the signal shaping and multiplexing, while Kerberos platform manages the events acquisition. The back-end operations are performed by Athena platform, that acts as global trigger and event builder for up to 4 Kerberos PCB. Athena provides a simple and low-cost multi-channel solution for the readout of large SDD arrays, measuring 175 eV FWHM resolution at 5.9 keV (tpeak = 4 μs) on the target detector and a 60 MB/s  maximum output data rate.

Keywords: Neutrino, DAQ, SDD, Spectroscopy, Multichannel
1:30 PM N-17-08

Belle II data readout with new PCIe board and comparison with present DAQ setup (#1369)

H. Purwar1, S. Yamada2, M. Bessner1, V. Gaur3, P. Robbe4, D. Charlet4, Q. D. Zhou5, O. Hartbrich1, Y. T. Lai6, D. Biswas7, K. Nishimura1, G. Varner1, M. Nakao2, T. Higuchi6, S. Y. Suzuki2, T. Kunigo2, R. Itoh2, P. Kapusta8

1 University of Hawaii at Mānoa, HEPG, Department of Physics and Astronomy, Honolulu, Hawaii, United States of America
2 High Energy Accelerator Research Organization (KEK), Tsukuba, Japan
3 Virginia Tech, Blacksburg, Virginia, United States of America
4 Université Paris-Saclay, CNRS/IN2P3, IJC Lab, Orsay, France
5 Nagoya University, Institute of Advanced Research (YLC), Kobayashi-Maskawa Institute (KMI), Aichi, Japan
6 University of Tokyo, Kavli Institute for the Physics and Mathematics of the Universe (IPMU), Tokyo, Japan
7 University of Louisville, Department of Physics and Astronomy, Louisville, Kentucky, United States of America
8 Institute of Nuclear Physics, PAN, Krakow, Poland


When SuperKEKB ultimately approaches its design luminosity, its primary particle detector, Belle II will need a faster data acquisition system. This demand will be met using more advanced readout electronics, raising the current throughput from ~1 Gbps to 10-100 Gbps. Belle II has planned an upgrade of its data acquisition system, starting in the summer of 2021 with two of its sub-detectors, namely the K-Long and Muon detector (KLM) and the imaging Time Of Propagation detector (iTOP). A dedicated team has been preparing for this upgrade and would like to share a part of this work, focusing on data acquisition and data quality with the new readout board (PCIe40). The development of the firmware and software libraries for the new readout board is now complete. It has been thoroughly tested on the actual detector as well as on independent test benches at KEK and Univ. of Hawaii (UHM). Through this submission, we would like to inform the scientific community of the data acquisition and data quality test results. A comparison of data quality between the upgraded electronics and existing Belle II DAQ set up using Common Pipeline Platform for Electronics Readout (COPPER) boards will also be made.

Keywords: Data acquisition, Particle beam measurements, PCIe40, Belle II DAQ upgrade

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