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Jan 29, 2022, 7:55:03 AM
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Application of SOI integration-type pixel sensors and up-to-date process (#80)
T. Miyoshi1, Y. Arai1, K. Hara6, T. Ishida7, Y. Kamiya4, T. Mibe1, S. Mitsui3, T. Inada4, R. Nishimura1, T. Sasaki3, T. Takayanagi1, T. Tsuboyama1, M. Yamada5, Y. Taha2
1 High Energy Accelerator Research Organization (KEK), Tsukuba, Japan
KEK (High Energy Accelerator Research Organization) SOI (Silicon-on-Insulator) group started development of SOI monolithic pixel sensor in 2005. In FY2009, general purpose integration-type pixel sensor, INTPIX4, was developed. The pixel size is 17 um, and the source follower amplifier is included in each pixel. In FY2014, another type of sensor, INTPIX8, was developed. Four gain settings can be selected, and the sensor can be adopted with both p-type and n-type wafer, and also with both single and double SOI wafer. Those sensors can be applied to experiments in various fields such as high energy charged particles experiment, X-ray and neutron imaging, electron microscopy, and muon experiment. Neutron sensor was fabricated by forming 10-B layer at the back side of the INTPIX4. Neutrons were irradiated in some neutron beam facilities and nuclear reaction spectra and neutron images were obtained. X-rays from synchrotron light were irradiated from the back side of the INTPIX4 to demonstrate residual stress measurement in steel material. Low energy electrons from electron microscope were irradiated from the back side of the INTPIX4 for feasibility study, and modulation transfer function and detective quantum efficiency was evaluated. The INTPIX8 was irradiated with muons in J-PARC center, and muon energy spectra were obtained and the dynamic range was evaluated. These sensors are planned to be upgraded, include minor changes to improve noise, reset time, and readout time in the INTPIX4, and include up-to-date process to reduce power consumption, enhance charge collection efficiency, improve radiation tolerance in the INTPIX8.
AcknowledgmentWe acknowledge the valuable advice and great work by the personnel of LAPIS Semiconductor Co., Ltd. This work was also supported through the activities of d.lab-VDEC, The University of Tokyo, in collaboration with Cadence Design Systems, NIHON SYNOPSYS G.K., and Mentor Graphics.
Keywords: SOI, Monolithic sensor, pixel sensor
High-Spatial and Time Resolution Vertex Detector for the ILC by 3D Stacking Technology based on SOI Pixel Sensor (#505)
M. Yamada1, S. Ono2, T. Tsuboyama2, Y. Arai2, I. Kurachi3, K. Hara4, H. Murayama4, S. Iwanami4, A. Takeda5, M. Motoyoshi6
1 Tokyo Metropolitan College of Industrial Technology (TMCIT), Information and Telecommunication Engineering Program, Tokyo, Japan
Three-dimensional stacking technology for monolithic pixel sensor is attractive to extend functionality of pixel circuit. It is usually a trade-off between small size pixel for high position resolution and implementation of complex pixel circuit. Our monolithic pixel sensor by using SOI technology ensures that two chips are stacked and the circuits of upper and lower chips are connected by Au micro bumps. This 3D stacking technology offers to extend the area to implement more complex signal readout circuitry. We have developed a 3D stacking SOI pixel sensor, SOFIST4, as a candidate vertex detector for the ILC experiment. ILC requires to reconstruct vertices with 3 μm resolution. SOFIST4 has achieved this high position resolution by utilizing the weighted center of charges. In addition, Beam bunches of the electrons and positrons collide about 1,300 times interval of 540 ns. Storing hit-by-hit timestamps is also necessary to reconstruct physics events with other subsystems. Furthermore, as there are multiple hits per pixel in 1 ms-long bunch train, multiple memories for hit, charge and timestamp are required. To perform all the functions in 20×20 μm2 of pixel, a pn junction, amplifier and comparator are implemented in lower pixel, hit, charge and timestamp memories are implemented in upper pixel. Outputs of amplifier and comparator are sent to upper memories via 3 μm diameter of Au micro bumps. We have already obtained 99.98% of bump connection yield on SOFIST4 90Sr β-ray tracks. Recent results of beam test with 120 GeV proton beam at Fermilab will be shown in this presentation. Hit correlation between SOFIST4 and telescope successfully observed.
This work was supported by VDEC, the Univ. of Tokyo in collaboration with Synopsys, Cadence Design Systems and Mentor Graphics Inc.. The beam test was performed with the support of the Japan/US Cooperation Program. The authors also acknowledge the work of LAPIS Semiconductor Co., Ltd. and Prof. M. Ikebe of Hokkaido Univ..
Keywords: 3D stacking, ILC, Monolithic Pixel detector, Silicon-on-Insulator, Vertex detector
Cross-talk and RTS noise characterization of 1- and 2-tier CMOS SPADs in a 150 nm process (#821)
L. Ratti1, 2, P. Brogi3, 2, G. Collazuol4, 2, G. - F. Dalla Betta5, 6, P. S. Marrocchesi3, 2, J. Minga1, 2, F. Morsani2, L. Pancheri5, 6, G. Torilla1, 2, C. Vacchi1, 2
1 Università di Pavia, Pavia, Italy
This paper presents the results from the characterization of single-tier and dual tier single photon avalanche diode (SPAD) arrays fabricated in a 150 nm CMOS technology. The chips under test contain SPADs with different size and active area and different avalanche quenching network, either passive or active. The tests were focused on the measurement of the dark count rate, with emphasis on the effects of optical cross-talk, in different operating conditions and for different sensor size and position in the array. Random telegraph signal (RTS) fluctuations in the dark count rate, and their dependence on the SPAD bias voltage, were also investigated.
Keywords: SPAD, CMOS, DCR, RTS, cross-talk
Characterization of Fully-Depleted MAPS Test Structures in 110nm CMOS Process (#904)
T. Corradino1, 2, G. - F. Dalla Betta1, 2, L. De Cilladi3, 4, C. Neubüser2, L. Pancheri1, 2
1 Università degli Studi di Trento, Dipartimento di Ingegneria Industriale, Trento, Italy
On behalf of the ARCADIA collaboration
Passive pixel arrays have been designed and tested to evaluate the characteristics and the dynamic performance of a group of samples produced with a novel technology for the fabrication of Monolithic Active Pixel Sensors (MAPS). The proposed technology relies on a commercial 110nm CMOS production process, where a low-voltage CMOS electronics is embedded on the sensor frontside. A p/n junction is formed between the high resistivity n-type region and the backside p+ region, thus allowing to reverse bias the sensors from the backside. Passive pixel arrays with 50 and 25 μm pixel pitch and 100-300 μm silicon substrates have been produced and characterized in order to extract the operating voltages of different pixel layouts and compare them with the values obtained from TCAD simulations. The charge collection dynamics of the pixel arrays has been evaluated by illuminating the samples in a test setup with a 1060 nm IR laser and amplifying the signal with a commercial wideband amplifier with 1 GHz bandwidth. A new production run includes passive pixel arrays with different pixel pitches and layouts optimized for timing applications. As the experimental results show a good agreement with TCAD simulations, we expect to obtain better dynamic performances from the new passive pixel arrays with the optimized layout.
AcknowledgmentThe research was carried out in the framework of the SEED and ARCADIA experiments funded by the Istituto Nazionale di Fisica Nucleare (INFN), CSN5.
The authors would like to thank LFoundry for the support.
Keywords: MAPS, Laser Characterization, CMOS, Radiation Detectors
Development of a Monolithic 166-Pixel SDD Detector for Electron Spectroscopy (#932)
M. Gugiatti1, 2, P. King1, 2, M. Carminati1, 2, S. Mertens3, 4, P. Lechner5, C. Fiorini1, 2
1 Politecnico di Milano, DEIB, Milan, Italy
This work presents the design and preliminary X-ray characterization of a detection module for electron detection applications. The module is based on a large 166-pixel monolithic Silicon Drift Detector (SDD) matrix. The detection system is developed in the context of the TRISTAN project, aiming at proving the existence of a keV-mass sterile neutrino by the measurement of the tritium beta-decay spectrum. A fully functional 166-pixel module, preceded by already developed 12- and 47-pixel prototypes, is a fundamental milestone for the TRISTAN project since the final focal plane detector will employ multiple 166-pixel tiles.
AcknowledgmentThis work is supported by Politecnico di Milano and Instituto Nazionale di Fisica Nucleare (INFN).
Keywords: Silicon Drift Detector, SDD, neutrino, beta decay, electron spectroscopy
Pixel chamber: a solid-state active target for 3D imaging of charm and beauty (#961)
A. Mulliri1, M. Arba2, P. Bhattacharya1, E. Casula1, C. Cicalò2, A. De Falco1, M. Mager3, D. Marras2, A. Masoni2, L. Musa3, S. Siddhanta2, M. Tuveri2, G. L. Usai1
1 University of Cagliari, Department on Physics, Monserrato (CA), Italy
Modern vertex detectors are based on cylindrical or planar layers of silicon sensors, generally immersed in a magnetic field. These detectors are used for precision measurements of the particles produced in the interactions and, in particular, of the decay products of those with a long mean life, such as open charm and beauty. Since the tracking layers are always few to tens of cm from the interaction point, this poses an ultimate limitation in the achievable resolution of the vertex position.
AcknowledgmentProject founded by Regione Autonoma della Sardegna
Keywords: Monolithic pixel sensor, ALPIDE, Vertexing, Particle tracking
Fabrication and Characterization of High Aspect Ratio Amorphous Silicon Based Microchannel Plates (#944)
S. Frey1, M. Beygi1, C. Ballif1, N. Wyrsch1
1 École Polytechnique Fédérale de Lausanne (EPFL), Institute of Microengineering (IMT), Neuchâtel, Neuchâtel, Switzerland
This contribution focuses on the fabrication of microchannel plates out of hydrogenated amorphous silicon (AMCPs). The flexible fabrication process and the semi-conducting nature of amorphous silicon gives these detectors unique advantages over conventional glass based microchannel plates (MCPs). One of the main advantages is the possibility to fabricate monolithic devices with high spatial and high temporal resolution. Optimization of the micro engineering processes have allowed the fabrication of devices with high aspect ratios up to 30. Simulations have shown that multiplication gains of over 2000 are possible with this new generation of AMCPs, making them viable alternatives for various applications such as detectors for positron emission tomography. The current work focuses on the fabrication and characterization of high aspect ratio devices. The multiplication gain is measured in the steady-state and transient regimes. Further characterization is done using the electron beam induced current technique.
This work was supported by the Swiss National Science Foundation (SNSF) under the Sinergia project on MEMS based Gamma Ray Detectors for Time-of-Flight Positron Emission Tomography (Grant number: 177165). All authors are with the Photovoltaics and Thin-Film Electronics Laboratory, Institute of Microengineering (IMT), Ecole Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel, Switzerland.
Keywords: Amorphous Silicon, Characterization, Microchannel Plates, Monolithic Integration, Positron Emission Tomography
SEM: Solid-state Electron Multiplier detector (#1405)
V. Coco1, E. L. Gkougkousis1, M. M. Halvorsen1, 2
1 CERN, EP-LBD, Geneva, Genève, Switzerland
A novel intrinsic gain sensor concept aimed at minimum ionizing particle (MIP) detection is presented, the solidstate electron multiplier (SEM). Contrary to doping induced gain region implementations (LGADs, APDs), amplifi-cation is achieved through potential difference in a GEM-like electrode structure embedded within the silicon bulk.Through multi-dimensional TCAD Synopsys simulations, various geometries are studied within the limitations im-posed by a MEMS fabrication technique. Effective gain, field, leakage current and capacitance values are discussedfor cell sizes in the range of 5 – 10 . A gain of more than 20 is demonstrated with time dispersion in the order of 20% at the imposed technological parameters. No radiation hardness limitations related to gain-layer deactivationare expected, allowing access to 1016 neq/cm2 fluence range. Plans for manufacturing of a proof of concept andsubsequent characterisation will be discussed.
AcknowledgmentThe authors would like to thanks the CERN EP-R&D program for its support
Keywords: Silicon sensor, intrinsic gain, ultra fast sensor, small pitch