IEEE 2021 NSS MIC

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High Resolution Circuits for Timing and Spectroscopy

Session chair: Grossmann , Martin (Paul Scherrer Institute (PSI), Villigen, Switzerland); Dragone , Angelo (SLAC National Accelerator Laboratory, Menlo Park, USA)
 
Shortcut: N-13
Date: Wednesday, 20 October, 2021, 9:15 AM - 11:15 AM
Room: NSS - 1
Session type: NSS Session

Contents

Click on an contribution to preview the abstract content.

9:15 AM N-13-01

Operation and performance of Timespot1: A high time-resolution 28-nm CMOS pixel read-out ASIC (#287)

A. Lai1, S. Cadeddu1, L. Frontini2, 3, V. Liberali2, 3, L. Piccolo4, 5, A. Rivetti4, A. Stabile2, 3

1 Istituto Nazionale Fisica Nucleare, Cagliari, Cagliari, Italy
2 Istituto Nazionale Fisica Nucleare, Milano, Milano, Italy
3 Università degli Studi di Milano, Milano, Milano, Italy
4 Istituto Nazionale Fisica Nucleare, Torino, Torino, Italy
5 Politecnico di Torino, Torino, Torino, Italy

Abstract

We present the test results of an ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 mm. The ASIC is conceived to be capable to read-out pixels with timing capabilities in the range of 20 ps (3D-trench silicon sensors). Each pixel is endowed with a charge amplifier, a leading-edge discriminator, and a Time-to-Digital-Converter, capable of time resolutions around 20 ps and maximum read-out rates (per pixel) of 3 MHz. The timing performance are obtained keeping the power budget of per pixel at the lower possible level. The ASIC is being tested in the laboratory concerning characterization of its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched 32x32 pixel sensor matrix and will be tested very soon under laser beam and Minimum Ionizing Particles (MIPs) in the laboratory and at test-beams. In this paper we present a description of the ASIC operations and the first results obtained from characterization tests concerning its performance in tracking measurements.

Acknowledgment

This work was supported by the Fifth Scientific Commission (CSN5) of the Italian National Institute for Nuclear Physics (INFN), Project TimeSPOT (CSN5 open-callcontest, 2017).

Keywords: Pixels with timing, hight time resolution, ASIC
9:30 AM N-13-02

Multi-Channel High-Resolution Digital-to-Time Pattern Generator IP-Core for FPGAs and SoCs (#335)

N. Corna1, E. Ronconi1, N. Lusardi1, F. Garzetti1, S. Salgaro1, A. Costa1, F. Ferraresi1, A. Geraci1

1 Politecnico di Milano, DEIB, MILANO, Italy

Abstract

In this paper, we present a novel Digital-to-Time Pattern Generator (DTC-PG) IP-Core, capable of generating several high-resolution digital waveforms in parallel, e.g. Pulse Width Modulation (PWM) patterns, compatible with Xilinx 28–nm 7-Series Field-Programmable Gate Array (FPGA) and System-on-Chip (SoC) devices. Compared to the state-of-the-art existing solutions, mainly implemented on Application-Specific Integrated Circuits (ASICs) devices, the advantages of the proposed DTC are the reduced hardware overhead, the high flexibility and, most importantly, reprogrammability, which make our IP-Core portable, more adaptable to different needs and quickly upgradable without the burden of a complete redesign of the system. The DTC output waveforms are tunable at different levels in real-time, and reach excellent performances thanks to the use of dedicated resources, widely available in modern FPGAs, namely Xilinx IDELAYE2 primitives. The working principle of our IP-Core is based on two signals, namely a coarse and a fine one: the latter is accurately delayed with respect to the former one, which serves as a reference. In this way, it has been possible to generate a variety of waveforms with tens of picosecond resolution and a Full-Scale Range (FSR), which is in the milliseconds range, maintaining the jitter below a few tens of picoseconds rms. The system is linear within a wide range of input values. The DTC IP-Core is designed for multi-channel solution, a 100-channel version it has been successfully validated on a custom board entirely developed at Politecnico di Milano, which hosts a Xilinx Artix-7 XC7A100TFTG256-2.

Keywords: Digital-to-Time Converter (DTC), Pattern Generator (PG), Pulse-Width Modulation (PWM), Field-Programmable Gate Array (FPGA), System-on-Chip (SoC).
9:45 AM N-13-03

Amplifier-discriminator ASICs to read out thin Ultra-Fast Silicon detectors for ps resolution (#617)

A. D. Martinez Rojas1, M. Ferrero1, F. Siviero1, M. Tornago1, R. Arcidiacono1, N. Cartiglia1, L. Menzio1, M. Mandurrino1

1 Istituto Nazionale di Fisica Nucleare, Torino, Turin, Italy

Abstract

This paper presents FAST2, a picosecond resolution front-end electronics to read out Ultra-Fast Silicon detectors (UFSD). The ASIC, designed in standard 110 nm CMOS technology, comprises 20 readout channels. The ASIC power rail is at +1.2 V, and its power consumption is 2.4 mW/ch. In our tests, the FAST2 ASIC, coupled to a UFDS with a capacitance of 3.4 pF, achieves timing jitters lower than 15 ps, at an input charge of about 15 fC. The experimental tests with an Sr90 beta source achieved a time resolution below 45 ps.

The worst case of Near-end and Far-end crosstalk due to the mutual capacitance achieves an amplitude of -23 dB at 50 W of load.

Keywords: Silicon radiation detectors, Timing Jitter, UFDS, Ultra-Fast electronics, CMOS technology.
10:00 AM N-13-04

Optimization of Charge Amplifier Reset Quiescent Current in LArASIC (#1073)

V. N. Manyam1, G. Deptuch1, S. Gao1, E. Tarpara1, N. Khan1, H. Chen1, G. Carini1

1 Brookhaven National Laboratory, Upton, New York, United States of America

Abstract

We present the optimization of the Charge Sensitive Amplifier (CA) in LArASIC, a 16-channel front-end in 180 nm CMOS, developed for the Deep Underground Neutrino Experiment (DUNE) far detector single-phase liquid argon (LAr) time projection chamber (TPC). The charge amplification is done in two stages; the first (CA1) and second (CA2) stage requires a small pre-biasing current (100 pA – 5 nA) or Reset Quiescent Current (RQI) sourced or sunk, respectively from its input, to keep the Adaptive Continuous Reset (ACR) circuit active. When it is too low, the DC operating point of CA will not be set up correctly, and when it is too high, the baseline shifts up. As the CA1 has a gain of 20, RQI gets multiplied by the same amount and a part of this current (16 times) needs to be subtracted for the best operation of the second stage. It was evidenced during measurements that all the channels were operating well at RT, with very little variability of CA1_RQI, whereas more than 10x unexpected variability was observed at liquid nitrogen (LN2). Owing to the improper subtraction of RQI in CA2 the second stage of CA was completely disabled at LN2 in a few channels. A test structure with several RQI subtraction and layout schemes is being fabricated to study the dependencies of the RQI subtraction precision. We present the design and layout methodology chosen to aid in the selection of the optimal RQI subtraction scheme for the LArASIC and highlighting challenges present in the design of circuits suitable for cryogenic operation where no foundry models, including mismatch information, exist.

AcknowledgmentThis manuscript has been authored by employees of Brookhaven Science Associates, LLC under Contract No. DE-SC0012704 with the U.S. Department of Energy.
Keywords: ASIC, Analog Front-End, Cryogenic Electronics, Deep Underground Neutrino Experiment (DUNE)
10:15 AM N-13-05

Digital Signal Processing Application Specific Intergared Circuit for 3D CdZnTe Gamma-Ray Detectors (#384)

M. Petryk1, Z. Chen1, S. Song2, D. Anderson1, M. Flynn2, Z. He1

1 University of Michigan, Department of Nuclear Engineering and Radiological Sciences, Ann Arbor, Michigan, United States of America
2 University of Michigan, Department of Electrical Engineering and Computer Sciences, Ann Arbor, Michigan, United States of America

Abstract

Recent improvements in CdZnTe detector energy resolution, imaging performance, and other capabilities have been spurred by algorithms leveraging new waveform-sampling readout electronics. However, processing of the sampled waveforms, as well as general control of the front end electronics, is accomplished by FPGAs and CPUs which increase the size and power consumption of these systems. To enable further reductions in system mass and power requirements, a new ASIC is designed at the University of Michigan. Intended to replace the FPGA and some of the CPU functions in current systems utilizing the H3DD-UM front end ASIC, the new ASIC digitizes the waveform samples output by the readout electronics and performs a number of digital operations to extract radiation interaction information. These operations include a per-channel rolling average baseline correction, preamplifier response deconvolution, several programmable digital filters, and amplitude and timing pickoff and interpolation logic. To perform these functions, the chip has an integrated low noise ADC, several digital filter channels and other special purpose processing circuitry, and interface logic. Implemented in a 65nm CMOS technology, the chip has an area of 17.6 mm2 and a power consumption of less than one watt.

AcknowledgmentThis material is based upon work supported by the Defense Threat Reduction Agency under Contract No. HDTRA119C0054. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Defense Threat Reduction Agency.
Keywords: 3D CZT, DSP, ASIC
10:30 AM N-13-06

A 2 Gbps custom LVDS transceiver for the ARCADIA project (#601)

M. Pezzoli1, 3, L. Gaioni2, 3, M. Manghisoni2, 3, L. Ratti1, 3, V. Re2, 3, G. Traversi2, 3

1 Università di Pavia, Ingegneria Industriale e dell'Informazione, Pavia, Italy
2 Università di Bergamo, Ingegneria e Scienze Applicate, Bergamo, Italy
3 INFN, Sezione di Pavia, Pavia, Italy

On behalf of the ARCADIA collaboration

Abstract

In the scope of the ARCADIA project, a set of custom LVDS driver and receiver have been fabricated in a \SI{110}{\nano\meter} CMOS technology for the first Main Demonstrator chip (MD1). The link is designed to provide a data rate of 2 Gbps and implements a control over the driver current in order to meet the needs of a low-power mode foreseen for the MD1. This paper will present the results from the characterization of the receiver/driver, in a loopback configuration, and compare them to simulations.

Keywords: DMAPS, CMOS, Transceiver, LVDS
10:45 AM N-13-07

Experimental characterization of the ORION analog processor, a multi-chip ASIC for x-/gamma-ray imaging spectroscopy (#758)

F. Mele1, I. Dedolli1, M. Gandola1, 2, M. Grassi3, P. Malcovati3, M. Fiorini4, R. Campana5, F. Fuschino5, C. Labanti5, G. Bertuccio1

1 Politecnico di Milano, Department of Electronics, Information and Bioengineering, Como, Italy
2 Fondazione Bruno Kessler, Trento, Italy
3 Università degli Studi di Pavia, Pavia, Italy
4 Istituto Nazionale di Astrofisica, Milano, Italy
5 Istituto Nazionale di Astrofisica, Osservatorio di Astrofisica e Scienza dello Spazio di Bologna, Bologna, Italy

Abstract

The first experimental results of the ORION CMOS analog processor, a highly customized Application Specific Integrated Circuit (ASIC) realized in a multi-chip architecture for the readout and signal processing of the X-Gamma Imaging Spectrometer (XGIS) on-board the THESEUS space mission, are presented. In
its foreseen flight version, the ORION multi-chip constellation will be responsible for the readout 12 800 Silicon Drift Detector (SDD) pixels, optically coupled to the top and bottom extremities of 6 400 CsI(Tl) scintillation bars. The ASIC integrates two dedicated analog processors for low-energy photons up to 20 keV
(X-channel) and high-energy photons up to 20 MeV (Gamma-channel), allowing a spectroscopy-grade resolution in the 4 decades energy
band (2 keV–20 MeV) of the XGIS. The presented prototype was bonded to two 25mm2 SDDs, and extensively characterized in terms of pulse shaping, pulse discrimination and stretching functionality, as well as linearity, dynamic range and spectroscopic resolution. An optimum Equivalent Noise Charge (ENC) at -20°C 24.3 el. r.m.s. on the X-channel (212 eV FWHM on Si), and 39.6 el. r.m.s. on the -channel (3.7 keV FWHM on CsI(Tl)) has been recorded.

Keywords: Nuclear microelectronics, Application Specific Integrated Circuits, Silicon Drift Detectors, Low-noise electronics, Low-power electronics
11:00 AM N-13-08

The MIRA Low Noise Charge Sensitive Amplifier for the Readout of Micro-Channel Plates (#908)

E. Fabbrica1, 2, M. Carminati1, 2, L. Quarteroni1, A. R. Mohammad Zaki1, D. Butta1, M. Uslenghi3, M. Pelizzo4, C. Fiorini1, 2

1 Politecnico di Milano, DEIB, Milano, Italy
2 INFN, Sezione di MIlano, Milano, Italy
3 INAF-IASF, Milano, Italy
4 CNR, Institute for Electronics, Information Engineering and Telecommunications, Padova, Italy

Abstract

Spectroscopic observations in the vacuum and extreme ultraviolet (VUV/EUV) spectral region are of great interest in various scientific fields, such as in Solar Physics, in the physics of interstellar medium and in the planetary exospheres studies.  The PLanetary Ultraviolet Spectrometer (PLUS) project aims at developing a novel dual channel EUV/VUV imaging spectrometer working in 55-200 nm spectral range. In this framework, the MIRA (MIcrochannel plate Readout Asic) ASIC has been designed. In this work, we present the MIRA ASIC charge sensitive amplifier (CSA) having a key role in achieving the low noise, high spatial resolution and high count rate ASIC requirements. The MIRA CSA features two selectable analog processing times, 130 ns or 277 ns (i.e. fast mode or slow mode), granting a count rate of 100 kcps. Moreover, it shows an equivalent noise charge ENC=21e- in fast mode. The low noise and high count rate requirements have been achieved by keeping a small occupation area (8µm x 14µm). Finally, we report a comparison between the MIRA CSA and a more common architecture such as the Krummenacher one, highlighting the advantages of the presented design in the ENC reduction.

Keywords: MCP, Analog Electronics, Integrated Circuits, CSA, Low Noise

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