2018 IEEE Nuclear Science Symposium and Medical Imaging Conference
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Analog & Digital Circuits II

Session chair: Fabris, Lorenzo, (Oak Ridge National Laboratory (ORNL), Nuclear Security and Isotope Tecchnology Division, Oak Ridge, US); Pratte, Jean-Francois, (Université de Sherbrooke, Canada)
Shortcut: N-35
Date: Thursday, 15 November, 2018, 10:20 AM
Room: Cockle Bay II
Session type: NSS Session


10:20 AM N-35-01

Petiroc2A: Charaterization and Experimental results (#1887)

S. Ahmad1, J. Fleury1, J. B. Cizel1, C. de la Taille2, N. Seguin-Moreau2, S. Gundacker3, 4, E. Auffray Hillemanns3

1 Weeroc, Palaiseau, France
2 Omega, IN2P3/CNRS/Ecole Polytechnique, Palaiseau, France
3 CERN, EP_CMX, Geneva, Switzerland
4 UniMIB, Milano, Italy


Petiroc2A is a 32-channel SiPM readout ASIC, which has been designed for applications requiring precise timing and energy measurement such as time-of-flight positron emission tomography. In this work, experimental results of Petiroc2A are presented.

Time and charge measurements for Petiroc2A have been performed at CERN with various SiPM models from FBK, Hamamatsu and Sensl. Scintillators used for the tests are mostly LSO:Ce,Ca crystals with dimensions ranging from 2x2x3mm3 up to 3x3x20mm3. Petiroc2A yields a single-photon time resolution (SPTR) of 90.68 ps FWHM when tested with FBK NUV 1x1mm2 SiPM. Meanwhile, the obtained coincidence time resolution (CTR) values when tested with FBK NUV-HD 4x4mm2 SiPM and 2x2x3mm3 LSO:Ce,Ca are 85.5 ps FWHM when measured externally and 127.27 ps FWHM when measured using the ASIC internal TDC. Using longer scintillators, 3x3x20mm3 LSO:Ce,Ca, and Hamamatsu S13360-3050PE SiPM with negative output, Petiroc2A yields a CTR value of 222.52 ps FWHM when measured with internal TDC. Using the same configuration outputting positive SiPM signal, Petiroc2A measured a nearly similar CTR, 225.32 ps FWHM. Similar setup yields, an energy resolution of 12.89% for 511 keV photon after correction when measured internally by Petiroc2A.

Keywords: ASIC, TOF, PET, SiPM
10:38 AM N-35-02

KLauS5: A 36-channel low-power silicon photomultiplier charge readout ASIC (#2099)

Z. Yuan1, K. Briggl1, H. Chen1, Y. Munwes1, H. - C. Schultz-Coulon1, W. Shen1, V. Koleva-Stankova1

1 Heidelberg University, Kirchhoff Institute for Physics, Heidelberg, Baden-Württemberg, Germany


The CALICE collaboration is developing concepts for highly granular calorimeter systems for future linear collider experiments. The high density of readout channels together with little space for cooling infrastructure limit the front-end power consumption to 25 uW per channel, which is achieved by power-pulsing the front-end electronics.  We present the development of KLauS, a 36-channel low-power mixed-mode ASIC for charge readout of Silicon Photomultipliers (SiPMs). Each channel consists of an analog front-end for charge integration and a 10/12-bit ADC to digitize the pulse height information.  Equivalent noise charge below 5 fC is measured, which is sufficient for single pixel signals of novel low-gain SiPMs. A dynamic range of 460 pC is achieved, allowing charge measurements over the full signal range of the SiPM sensors. Besides, a coincidence time resolution (CTR) of 393 ps FWHM is measured with 3.1*3.1*15 mm3 LYSO crystals and 50 um pixel pitch MPPCs, which will provide a low-power readout solution for small animal Positron Emission Tomography (PET) systems. Design details and measurement results will be presented.

Keywords: ASIC, SiPM, power-pulsing
10:56 AM N-35-03

GAMMA SiPM ASIC: Performance Assessment and Improved Design with 87dB Dynamic Range (#2407)

G. L. Montagnani1, 2, L. Buonanno1, M. Grandi1, M. Carminati1, 2, C. E. Fiorini1, 2

1 Politecnico di Milano, DEIB, milano, Italy
2 INFN, Milano, milano, Italy


Recently-developed high density SiPMs make today a high dynamic range (DR) electronic readout a necessity in different applications, especially in high-resolution gamma spectroscopy with high-performance scintillators such as LaBr3. GAMMA-8 was a chip designed to cope with large DR requirements, thanks to a smart auto-gain switching, while maintaining low noise and high tolerance to disturbances. Double sampling capability of the ASIC allows the exploitation of the chip also for CLYC readout and neutron discrimination. GAMMA-16 is the upgraded version of the aforementioned chip with improved DR (87dB), Full Scale Range and single photon triggering capabilities. This work will focus on an extensive analysis performed with the first release of this ASIC to understand its criticalities and assessing its performance. The systematic experimental characterization will be presented along with optimized design guidelines. The experimental results obtained with an upgraded and refined version of the chip that profits of those relevant improvement in a 16-channel format, compatible with large arrays of SiPMs, will be presented at the conference.

Keywords: SiPM, Labr3, ASIC
11:14 AM N-35-04

SiREAD: A 32 Channel 1 GSa/s Waveform Sampling and Readout System-on-Chip for High Density Detectors (#2820)

I. Mostafanezhad1, L. Macchiarulo1, G. Varner2, B. Rotter1, D. Uehara1, C. Chock1

1 Nalu Scientific, LLC, Honolulu, Hawaii, United States of America
2 University of Hawaii, Physics, Honolulu, Hawaii, United States of America


This paper presents the development of a novel waveform sampling ASIC (SiREAD), optimized for high density light detectors, such as Silicon Photomultiplier (SiPM) or MA-PMTs. The SiREAD is capable of analog signal conditioning and up to 1 Gigasample/sec waveform sampling with the ability to service 32 channels. The SiREAD is a System-on-Chip with built-in SiPM biasing, calibration, and digitization control on the analog side and feature extraction and digital signal processing on the digital side so that it is user friendly and robust to pileups. The SiREAD device also has a deep sampling buffer making it suitable for large and high rate NP experiments such as the Relativistic Heavy Ion Collider and the future Electron Ion Collider. In this paper we cover details of the design, fabrication and preliminary test results.

Keywords: Front-end circuits, Waveform Sampling, Switched capacitor array, system-on-chip, High density detector
11:32 AM N-35-05

CDP1: A Data Concentrator Prototype for Deep Underground Neutrino Experiment (DUNE) (#2357)

S. Miryala1, D. Braga1, D. Christian1, G. W. Deptuch1, P. Gui2, J. R. Hoff1, S. Holm1, X. Wang2

1 Fermi National Accelerator Laboratory, Electrical Engineering, Batavia, Illinois, United States of America
2 Southern Methodist University, Electrical Engineering, Dallas, Texas, United States of America


The design, test and power analysis of a first COLDATA Prototype (CDP1) design in 65nm process for the Long Baseline Neutrino Facility (LBNF) and the Deep Underground Neutrino Experiment (DUNE) is presented. CDP1 is a prototype for the COLDATA chip, a data concentrator operated in liquid argon. The data concentrator sends the recorded data from multiple front-end integrated circuits out of the cryostat over a ~30m long coaxial cables. CDP1 hosts both analog and digital blocks, like LVDS drivers and Receivers, Serializer, Phase Locked Loop (PLL), I2C for slow control, fast command receiver and calibration logic. The test measurements of the chip are carried out at room temperature and at cryogenic temperature (77k). The test measurements are in good agreement with the simulation results.

Keywords: Cryogenic Electronics, Data Concentrator, Power Integrity Analysis
11:50 AM N-35-06

An Ultra-Low-Noise LDO Regulator in 65 nm for Analog Front-End ASICs in Cryogenic Environment (#2670)

W. Hou1, S. Li2, G. de Geronimo1, M. Stanacevic1

1 Stony Brook University, Department of Electrical and Computer Engineering, Stony Brook, New York, United States of America
2 Brookhaven National Laboratory, Instrumentation Division, Upton, New York, United States of America


Low dropout (LDO) voltage regulators, which provide a clean supply for analog and mixed-signal systems, are essential to low-noise front-end electronics in high energy physics experiments and beyond. This paper analyzes the noise sources in an LDO where the input referred noise of the error amplifier is the dominant noise source. Implemented in 65 nm technology, the LDO presented here regulates a noisy 1.5 V supply and outputs a stable and low-noise nominal 1.175 V voltage with load current ranging from a few milliamp up to 150 mA. The design achieves higher than 75% power efficiency at both room and cryogenic temperatures with more than 40 dB power supply rejection up to 500 kHz. The simulated RMS noise from 10 Hz to 100 kHz is less than 2 µV at room temperature and less than 1 µV at 77 K. The regulator requires an external capacitance of 50 µF for stability. A number of next-generation detectors can greatly benefit from having this voltage regulator directly integrated in the front-end application-specific integrated circuits (FE-ASICs) working at room and cryogenic temperatures.

Keywords: Ultra-Low-Power, LDO, Cryogenic, Power Efficient