IEEE 2017 NSS/MIC/RTSD ControlCenter

Online Program Overview Session: N-35

To search for a specific ID please enter the hash sign followed by the ID number (e.g. #123).

DAQ and Analysis Systems II

Session chair: Stefan Ritt; Martin L. Purschke
 
Shortcut: N-35
Date: Thursday, October 26, 2017, 10:20
Room: Regency VII
Session type: NSS Session

Contents

10:20 am N-35-1 Download

Hardware Implementation of a Fast Algorithm for the Reconstruction of Muon Tracks in ATLAS Muon Drift-Tube Chambers for the First-Level Muon Trigger at the HL-LHC (#2953)

S. Abovyan1, V. Danielyan1, M. Fras1, P. Gadow1, O. Kortner1, S. Kortner1, H. Kroha1, F. Müller1, S. Nowak1, R. Richter1, K. Schmidt-Sommerfeld1

1 Max-Planck-Institut fuer Physik, Munich, Bavaria, Germany

Content

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first level triggers are essential for the physics programme of the ATLAS experiment at the HL-LHC where the instantaneous luminosity will exceed the LHC Run 1 instantaneous luminosity by almost an order of magnitude. The ATLAS first level muon trigger rate is dominated by low momentum muons, selected due to the moderate momentum resolution of the resistive plate and thin gap trigger chambers. This limitation can be overcome by including the data of the precision muon drift tube (MDT) chambers in the first level trigger decision. This requires the fast continuous transfer of the MDT hits to the off-detector trigger logic and a fast track reconstruction algorithm performed in the trigger logic.

In order to demonstrate the feasibility of reconstructing tracks in MDT chambers within the short available first-level trigger latency of about 3 µs we implemented a seeded Hough transform on the ARM Cortex A9 microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beam data recorded in CERN's Gamma Irradiation Facility. We could show that by using the ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4 floating point operations in parallel the challenging latency requirement can be matched.

Keywords: Muon, Trigger, ATLAS, Drift tube, HL-LHC, LHC, giu
10:38 am N-35-2

Multi-Channel Time-to-Digital Converter for MTCA.4 Standard in FPGA (#1523)

N. Lusardi1, F. Garzetti1, M. Guštin2, J. Marjanovič2, A. Geraci1

1 Politecnico di Milano, DEIB - Department of Electronics, Milano, Italy
2 CAEN ELS s.r.l., Basovizza (TS), Italy

Content

In this contribution, we present a high-resolution and multi-channel Time-to-Digital Converter (TDC) realized on a proprietary application-oriented FPGA-Mezzanine-Card (FMC) connected with a general-purpose Advanced-Mezzanine-Card (AMC) carrier board for MTCA.4 standard that hosts a Xilinx Virtex5 70T in 67 nm technology with 10000 slices.

The system allows to measure in parallel 16 input channels with resolution of 10 ps, 10.7 s full-scale range, and precision less than 15 ps r.m.s. Moreover, each channel supports multi-hit measure rate up to 10 MHz keeping constant the performance.

The TDC is implemented into the FPGA device hosted in the FMC daughter board that is a 28 nm Serie7 Xilinx Artix®-7 XC7A200T. The inputs to the TDC are signals conditioned by an analog front-end composed of 16 comparators, whose thresholds are programmable via software. The measurement is totally performed and decoded into the FPGA. Settings of the TDC and communication of the measure results are performed via FMC to the carrier board and read-out to the AMC through a PCI-Express link.

Keywords: MTCA.4, FPGA, TDC, FMC, PCI-E
10:56 am N-35-3

Measurement of Proton Beam Generated β+ Radioactivity by Use of All-digital PET Detectors (#2423)

M. Gao1, N. D’Ascenzo1, C. - M. Kao5, Y. Hua1, X. Lyu1, I. - T. Hsiao2, 3, C. - Y. Li2, 3, H. - H. Chen3, J. - H. Hong3, T. - C. Yen3, Q. Xie1, 4

1 Huazhong University of Science and Technology, Wuhan, China
2 Chang Gung University, Taoyuan, China
3 Chang Gung Memorial Hospital, Taoyuan, China
4 Wuhan National Laboratory for Optoelectronics, Wuhan, China
5 The University of Chicago, Chicago, United States of America

Content

One key issue in proton beam therapy is to ensure precise delivery of the concentrated radiation dose to the target. A promising method that is under active study and development is the use of position emission tomography (PET) for range verification or monitoring. In this work, we test the use of a digital PET system developed on the basis of a Plug-and-Imaging architecture for a proton therapy system. We analyze technical features of the proposed PET technology and experimentally demonstrate the possibility to imaging positron decays in a phantom immediately after proton irradiation. The experiment results agree with the expectation according to the physical properties of proton beam interaction with hydrocarbons.

Keywords: all-digital PET detector, Plug-and-Imaging platform, Proton Therapy
11:14 am N-35-4 Download

A Data Acquisition system for a Beam-tagging Hodoscope used in Hadrontherapy Monitoring (#2483)

X. Chen1, J. - P. Cachemiche2, C. Caplan Cheble Pimenta2, L. Caponetto1, D. Dauvergne3, R. Della Negra1, M. Fontana1, G. - N. Lu4, C. Morel2, M. Rodo Bordera2, E. Testa1, Y. Zoccarato1

1 Université de Lyon 1, Institut de Physique Nucléaire de Lyon,IN2P3/CNRS, UMR 5822, VILLEURBANNE, France
2 Aix-Marseille Univ, CNRS/IN2P3, CPPM, Marseille, France
3 Université Grenoble-Alpes, Laboratoire de Physique Subatomique et Cosmologique,IN2P3/CNRS, UMR 5821, Gronoble, France
4 Université de Lyon 1, Institut de Nanotechnologies de Lyon,CNRS ,UMR 5270, VILLEURBANNE, France

Content

For ion-range monitoring in hadrontherapy, we propose a high throughput data acquisition (DAQ) system associated with a beam hodoscope to allow spatial and temporal labelling. The hodoscope consists of an array of scintillating fibers (BCF 12, 1×1mm2 square section) in vertical and horizontal directions, which are coupled to multi-anode photomultipliers (H-8500) via optical fibers. Two prototypes have been built with 2×32 (small size) and 2×128 (large size) fibers. Depending on the type of hodoscope associated, the proposed DAQ system contains one or eight multi-channel hodoscope readout boards. It also includes a Micro Telecommunications Computing Architecture (µTCA) module (with 3-Gbit/s optical links to the hodoscope readout boards) and a PC. The µTCA module mainly consists of an AMC40 readout board. Each hodoscope readout board incorporates two 32-channel readout ASICs, a signal-processing & control FPGA and a 3-Gbit/s optical transceiver to the µTCA’s AMC40 board. It has been designed to meet system requirements on 1-mm spatial resolution, 1-ns temporal tagging resolution and 100-MHz counting rate capability. The AMC40 board features 36-channel bidirectional optical links, as well as a 1-Gbit/s Ethernet link to the PC. The DAQ system supports two types of triggers: a self-trigger and two external triggers. To optimize data throughput of optical transmission between hodoscope readout board and the AMC40 one, we have defined a specific protocol, by using only basic 8b/10b encoding, and fully exploiting specific control symbols to distinguish different types of frames (control, monitoring, and data). The operation of the hodoscope readout board has been validated by bench test, while the AMC40 has already been used in LHCb experiments at CERN. The optical data transmission between boards has also been verified by tests. A beam test on the DAQ system has been scheduled and is being prepared.

Keywords: Hadrontherapy, hodoscope, data acquisition system, µTCA, multi-channel readout board, High-throughput optical transmission
11:32 am N-35-5

Upgrade of the ATLAS Monitored Drift Tube Frontend Electronics for the HL-LHC (#2497)

J. Zhu1, J. Wang1

1 University of Michigan, Ann Arbor, United States of America

Content

To cope with large amount of data and high event rate expected from the planned High-Luminosity LHC (HL-LHC) upgrade, the ATLAS monitored drift tube (MDT) readout electronics will be replaced. In addition, the MDT detector will be used at the first-level trigger to improve the muon transverse momentum resolution and reduce the trigger rate. A new trigger and readout system has been proposed. Prototypes for two frontend ASICs and a data transmission board have been designed and tested, and detailed simulation of the trigger latency has been performed. We will present the overall design and focus on latest results from different ASIC and board prototypes.

Keywords: LHC, ATLAS, muon detector, drift tube, readout
11:50 am N-35-6 Download

The Readout of the sPHENIX Tracking System (#2949)

M. L. Purschke1

1 Brookhaven National Lab, Physics, Upton, New York, United States of America

on behalf of the sPHENIX Collaboration.

Content

The sPHENIX Collaboration at RHIC is upgrading the PHENIX detector in a way that will enable a comprehensive measurement of jets in relativistic heavy ion collisions. The upgrade will give the experiment full azimuthal coverage within a pseudorapidity range of -1.1 < \eta < 1.1.

 We have presented the status of the sPHENIX project at the last conference. Since then, we have selected the technologies for the tracking system, which will consist of a silicon detector based on MAPS (Monolithic Active Pixel Sensors), followed by an Intermediate Tracker (INTT), and then by a TPC. With the exception of the INTT, which is based on the former PHENIX Forward Vertex Detector and also re-uses the readout technology, both the MAPS detector and the TPC introduce new readout hardware and strategies.

In order to achieve high event rates, the TPC needs to be read out in continuous, or streaming, mode, without the use of a gating grid. The resulting continuously sampled waveforms of the TPC sensors must then be processed and correlated with the actually triggered events of the full detector.

Since the TPC is using the ALICE Sampa ASIC, one of the possible readout cards is the ALICE "Common Readout Unit" (CRU). We are also looking into a card in use in the ATLAS experiment, called "FELIX". Both cards are PCIe-based and have a large number (up to 48) of fiber inputs to connect to the front-end cards, and a powerful FPGA for waveform processing.

The MAPS detector will use the eventually chosen technology for its readout as well.

We will present the envisioned design of the streaming readout, and explain the challenges with the high data rates generated by this readout method, which could reach as much as 80 GBit/s. We will show the design of our data acquisition to cope with those data rates, and present the status of the ongoing R&D. By the time of the conference, we will likely have a number of prototype setups, and some actual performance data.

Keywords: sPHENIX, DAQ, Streaming readout