Effect of gamma irradiation on leakage current in CMOS readout chips for the ATLAS Upgrade Silicon Strip Tracker at the HL-LHC. (#1919)
S. Stucci1, D. Lynn1, R. Burns1, J. Kierstead1, A. Tricoli1, P. Kuczewski1, G. van Nieuwenhuizen1
1 Brookhaven National Laboratory, Physics, Upton, New York, United States of America
The increase of the leakage current of NMOS transistors in certain 130 nm CMOS technologies during exposure to ionizing radiation needs special consideration in the design of detector systems, as this can result in large increases in current and power dissipation. As part of the R&D program for the upgrade of the ATLAS inner tracker for the High Luminosity upgrade of the LHC at the CERN laboratory, a dedicated set of irradiations has been carried out with the 60Co gamma source at the Brookhaven National Laboratory. Measurements will be presented that characterize the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips, as observed by other experiments. The variations of the current as a function of time and total ionizing dose have been studied under different conditions, such as dose rate, temperature and power applied to the chip. The ranges of variation of dose rates and temperatures have been set to be as close as possible to those expected at the High Luminosity LHC, i.e. in the range 0.6 krad/h - 2.5 krad/h and between -10 °C and +10 °C. Some of the chips under test were pre-irradiated with high doses of X-rays at Rutherford Appleton Laboratory in order to study the different effect of radiation on un- and pre-irradiated devices. The results show unique features, e.g. current peak value and current peak time dependence on dose rate, no change in current when temperatures are raised from -10 °C to +10 °C after the current peak is reached and no increase in current on pre-irradiated chips. These results provide valuable information for the understanding of the underlying mechanisms responsible for radiation damage in transistors and detector readout chips. Models that attempt to parameterize the leakage current under different environmental conditions and how they fit to experimental data will be also presented.
Keywords: NMOS transistor, radiation hard, increase in digital current, radiation damage, TID bump
The PixFEL front-end for X-ray imaging in the Grad-TID environment of next generation FELs (#3480)
1 University of Pavia and INFN, Department of Electrical, Computer and Biomedical Engineering, Pavia, Italy
On behalf of the PixFEL collaboration
In the framework of the PixFEL project, a processing channel for pixel sensor readout has been designed and fabricated in a 65 nm CMOS technology. The detector under development is intended for application to coherent X-ray diffraction imaging (CXDI) at the next generation free electron lasers (FELs). Especially in the detector region around the hole for the unscattered photon beam, pixels will be subjected to huge doses of ionizing radiation, in the order of 100 Grad. The total ionizing dose (TID) for the front-end electronics is significantly reduced by the shielding effect of the detector, but is still anticipated to be as large as a few Grad. This paper will investigate the performance degradation in the PixFEL front-end circuit after exposure to large X-ray doses, up to 1 Grad. The final level will be reached through a few intermediate steps for the purpose of monitoring the trend in the radiation induced drift of the main parameters, such as gain, noise, response time and non linearity.
Keywords: Ionizing radiation damage, CMOS front-end, X-ray diffraction imaging, Low noise processing
Performance of a Novel Redundant-Configuration Scrubbing Technique for SRAM-based FPGAs (#2097)
R. Giordano1, 2, S. Perrella1, 2, V. Izzo2, G. Milluzzo3, 4, A. Aloisio1, 2
1 University of Naples "Federico II", Physics Dept., Naples, Italy
SRAM-based FPGAs are widely adopted in trigger and data acquisition systems of HEP detectors for implementing fast logic due to their re-configurability, large real-time processing capabilities and embedded high-speed serial IOs. These devices are sensitive to radiation-induced upsets, which may alter the functionality of the implemented circuit. Presently, their usage on-detector is limited and there is a strong interest in finding solutions for improving their tolerance to radiation-induced upsets.
We present the performance of a novel configuration-redundancy generation and scrubbing technique for SRAM-based FPGAs. The discussed technique leads to a significant power saving with respect to other solutions in the literature. The power consumption penalty related to standard techniques based on modular redundancy can reach 200%, while tests on benchmark designs show that for our approach this parameter can be as low as 60%. Moreover, our technique is portable over several Xilinx FPGA families, including latest and older ones. Our solution does not require neither the usage of external memories nor third-party layout tools. We show a demonstrator of our solution applied to a benchmark design implemented in a Xilinx Kintex-7 FPGA. In order to prove the effectiveness of the solution, we present results from 62-MeV proton irradiation tests performed at INFN Laboratori Nazionali del Sud (Catania, Italy).
Keywords: Radiation effects, single event effects, single event upsets, multiple bit upsets, soft errors, FPGA, radiation testing, proton.
Single Event Upset tests for a CMOS 0.35 um front-end and readout electronics for high-flux particle detectors (#3385)
F. Fausti1, 2, G. Mazza2, A. Attili2, S. Giordanengo2, O. A. Hammad2, 3, L. Manganaro2, 3, V. Monaco2, 3, R. Sacchi2, 3, A. Vignati2, R. Cirio2, 3
1 Politecnico di Torino, Dipartimento di Elettronica e Telecomunicazioni, Torino, Italy
The Single Event Upset rate of a 64 channels integrated circuit, designed in CMOS 0.35 um technology, has been measured and analyzed at the SIRAD facility of the Italian National Institute for Nuclear Physics (INFN). The chip, named TERA09, is a current to frequency converter designed to readout monitor chambers in particle therapy. In this field, the accelerator development is moving toward compact solutions providing high-intensity pulsed-beams. The TERA09 chip is capable to operate in a wide input current range, from few nA to hundreds of μA, with linearity deviations in the order of few percent. The chip is designed to be located aside of the monitoring chambers, far from the therapeutic beam, and no protection from data corruption from single events was implemented in its design. However, considering the relatively large area of the chip covered by data registers and the secondary neutrons field produced during the irradiation, the potential exposure to data corruption by Single Event Effect phenomena need to be addressed. The aim of the tests at SIRAD is to study the upset rate as a function of the energy deposited by single events by irradiating the chip with ions of different LET. From the analysis of the data it is possible to predict the single event effect cross-section in a clinical environment and estimate the readout failure probability in a real application scenario.
Keywords: Radiation damage; Single Event Effect; Front-end electronics.
Radiation Hard GaNFET High Voltage Multiplexing (HV-Mux) for the ATLAS Upgrade Silicon Strip Tracker (#1511)
2 Cambridge University, Cavendish Institute, Cambridge, United Kingdom of Great Britain and Northern Ireland
The High Luminosity upgrade to the Large Hadron Collider (HL-LHC) requires a replacement of the present ATLAS inner tracker with an all-silicon inner tracker (ITk). The outer radii of the ITk will consist of groups of silicon strip sensors mounted on common support structures. Lack of space for additional cabling will require groups of sensors to share a common HV bus (-500 V). This creates a need to remotely disable a failing sensor from the common HV bus to permit continued operation of the other sensors. We have developed circuitry consisting of a Gallium Nitride Field-Effect transistor (GaNFET) and an HV Multiplier circuit to disable a failed sensor. The devices have been shown to survive radiation doses as high as 1 x 1016 neutrons/cm2 and ionizing doses over 200 Mrad. We will present the HV Mux circuitry and show irradiation results on individual components with an emphasis on the GaNFET results with neutrons, protons, pions, and gammas. We will present a dual-stage variation of the HV Mux that will permit operation to -700 V as this voltage may become a final requirement for the strip detector. We will also discuss the reliability of the HV Mux circuitry and show plans to ensure reliability during production.
Keywords: high voltage, multiplexing, ATLAS
Radiation Hard DC-DC Converter for Large Collider Experiments (#4047)
A. Hegde1, Y. Long2, J. Kitchen1, P. K. Bikkina2, E. O. Mikkola2
1 Arizona State University, Tempe, Arizona, United States of America
High efficiency, radiation hard, hybrid GaN and CMOS integrated module DC-to-DC converter has been designed. The integrated, compact, low-mass, single-module DC-DC converter solution has an input voltage of 18V regulated down to an output voltage of 1.4V, with 5A maximum load current. It exhibits >80% efficiency. Discrete GaN transistors are used for the power stage, and the controller circuitry and power device drivers are integrated on a 0.35um CMOS chip. Radiation hardening by design (RHBD) techniques have been implemented and the goal is that the converter functions at total ionizing dose (TID) levels ≥150 megarad(Si). The first prototype of the converter has been designed, fabricated and tested and is discussed in this paper.
Keywords: power management, radiation effects, radiation hardening by design, DC-DC converter