ULN1C: An Ultra-Low Noise Readout ASIC for X-ray CCD Adopting ΣΔ-CDS Technique (#4236)
B. Lu1, 2, Y. Chen1, T. Yi4, Z. Hong4, Y. Zhou2, 3
1 Institute of High Energy Physics, Chinese Academy of Sciences, Key Laboratory of Particle Astrophysics, Beijing, Beijing, China
This work presents the development of a single-channel correlated double sampling (CDS) ASIC, named ULN1C, targeting the readout of X-ray CCDs for applications in the fields of both X-ray spectroscopy and imaging. The ASIC adopts two time-interleaved pre-modulated 3-order 1-bit incremental ΣΔ modulators (SDMs) and a 5-order 228-point truncated cascade of integrated comb (TCIC) filter. It features both optimized sampling strategy for SDMs and decimation scheme for TCIC filter as well as a low-noise analog front-end (AFE) in order to achieve ultra-low-noise and low-power performances. ULN1C ASIC is fabricated with GlobalFoundries 0.35μm 2P4M CMOS process and occupies a chip area of 2992×2018 μm². When tested standalone, the ASIC achieves a maximum 40ppm integral nonlinearity (INL) and 10.8μV input-referred readout noise under 100kHz pixel rate (PR) within the effective input dynamic range of 60mVpp and only consumes 18mW from a single 3.3V supply voltage; When tested with the target X-ray CCD—CCD236 using a 1μCi 55Fe radioisotope, by cooling down the CCD to in the vicinity of 160K, the ASIC achieves energy resolutions (FWHM) as 132eV@5.9keV and 129eV@5.9keV under 100kHz and 50kHz PRs, respectively. The total readout noises are only 4.5e- and 5.2e-, respectively.
Keywords: CDS, X-ray CCD, Sigma-Delta, TCIC, ASIC
HEXID2: A Low-Power, Low-Noise Pixel Readout ASIC for Hyperspectral Energy-Resolving X-Ray Detectors (#1704)
S. Li1, G. De Geronimo2, J. Fried1, D. Pinelli1, A. Kuczewski1, D. P. Siddons1, B. Beheshtipour3, R. Bohse3, H. Krawczynski3
1 Brookhaven National Laboratory, Upton, New York, United States of America
We present a low-power, low-noise prototype pixel readout application specific integrated circuit (ASIC) for hyperspectral energy-resolving X-ray imaging detectors. The ASIC provides 16-by-16 channels to read out positive and negative charges from 16-by-16 hexagonal silicon or CZT detector arrays, at a pitch size of 250 µm, to achieve good spatial resolution and the ability to record the energy of a detected photon as well as its position. The readout is done by bump-bonding the anodes to the inputs of the ASIC. Each channel of the ASIC provides low-noise charge amplification, high-order shaping with baseline stabilization, discrimination, extraction of amplitude (with neighbour channels), multiplexing, and dissipates ~0.6 mW. A smart readout of the triggered pixel and its adjacent six pixels in the hexagonal configuration allows reconstruction of events with charge sharing correction, and can be used to estimate the depth of the photon interaction and to suppress background events. The target equivalent noise charge (ENC) is ~10 electrons for silicon detector pixel and ~15 electrons for CZT detector pixel.
Keywords: low-power, low-noise, ASIC, X-ray detector, CZT detector
The 4k Pixel Readout ASIC with Local Amplitude Digitization and Storage for the DSSC X-Ray Detector at the European XFEL (#3034)
F. Erdinger1, C. Fiorini2, P. Fischer1, A. Grande2, P. Kalavakuru4, M. Kirchgessner1, M. Manghisoni5, K. Hansen4, M. Porro3, C. Reckleben4, J. Soldat1
1 Heidelberg University, Institute for Computer Engineering, Heidelberg, Germany
We present the full format 14.9 x 14 mm2 pixel readout ASIC for the 1 MPixel X-ray camera developed by the DSSC collaboration for the European XFEL. The ASIC contains front-ends which are customized for the DSSC specific DEPFET APS sensor comprising signal compression as well as a passive mini-SDD. The fast pulse frequency of up to 4.5 MHz at the European XFEL requires local storage of the detected signals in the pixels. The data is transferred off the chip in 99.4 ms gaps in between the XFEL bursts of 2880 pulses. The DSSC detector is tailored for the low energy experiments (0.5 - 6 keV) at the European XFEL. The ASIC processing chain includes per pixel an analog front-end including a filter with trapezoidal weighting function, an 8-9 bit single slope ADC and an SRAM with a capacity of 800 words. Known bad events can be vetoed on the fly. The chip comprises 64 x 64 pixels of 229 x 204 um2 which are mated to hexagonal sensor pixels. The ASIC further includes biasing and high precision injection circuits for all parts of its signal processing chain. The integration of a full digital control block makes it completely self contained requiring only a simple digital interface for control. The chip is operated with power cycling of most supplies to benefit from the low duty cycle of 1/100 of the European XFEL. The chip architecture and measurements from both front-end variants are presented.
Keywords: XFEL, DSSC, DEPFET, CSA, SDD, pixel detector, readout electronics, multi channel ADC, SRAM
Development of a Charge Sensitive Amplifier with Offset-Cancelled V to I Converter for mini-SDD XFEL Detector (#3022)
A. Grande1, 2, C. Fiorini1, 2, F. Erdinger3, P. Fischer3, M. Porro4
1 Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Milan, Italy
In this work we present the study and the experimental results on a front-end stages for the mini-SDD pixel sensors of the DSSC detector for photon science applications at the European XFEL GmbH in Hamburg. The detector must be able to cope with an image frame rate up to 4.5 MHz and with a dynamic range up to 10^4 photons/pixel/pulse for a photon energy of 1 keV. Among the different studied front-ends for this detector, we present here a Charge Sensitive Amplifier (CSA) solution with a very simple V to I converter stage, which allows the self-cancelling of the offset current flowing between the CSA and the filter. The CSA is compatible with the same ASIC architecture (filter, ADC etc...) already designed for the DEPFET detector. Two versions of the CSA, with linear and compressed response, are here presented. Preliminary measurements on the linear version of the CSA have demonstrated the capability of the proposed self-cancelling solution, good noise performance with an ENC of 65e- rms at 4.5 MHz frame rate and a linearity error lower than 0.25 % of the complete channel.
Keywords: DSSC, DEPFET, CSA, mini-SDD, XFEL
An Ultra Low-Noise Front-End ASIC for High-Purity Germanium Point-Contact Detectors in Liquid Nitrogen (#3258)
S. Li1, G. De Geronimo2, P. Barton3
1 Brookhaven National Laboratory, Upton, New York, United States of America
We present an ultra low-noise front-end application specific integrated circuit (ASIC) developed for high purity germanium (HPGe) p-type point-contact (PPC) detectors operating in liquid nitrogen (LN) for low background experiments. The ASIC provides low-noise charge amplification for an input range of 100 eV to 50 keV, anti-aliasing filtering while preserving a minimum of ~60 ns event rise time, an analog output buffer to drive the cold/warm interface, and is fabricated in a commercial 180-nm CMOS technology. Given a full depletion capacitance of the HPGe PPC as low as ~100 fF, the ASIC achieves the lowest possible equivalent noise charge (ENC) ~3.9 electrons at 2 µs at LN temperature, and dissipates ~9 mW.
Keywords: HPGe PPC detector, low-noise ASIC, liquid nitrogen operation
1.2 GeV dynamic range VLSI charge preamplifier for nuclear physics experiments (#3084)
A. Castoldi1, 2, C. Guazzoni1, 2, T. Parsani1, 2, G. Cardella3, N. S. Martorana4, 3
1 Politecnico di Milano, DEIB, Milano, Italy
In order to upgrade the performance of the frontend of the silicon layers of the FARCOS telescopes especially in terms of the available dynamic range to study the PIGMY dipole resonance in 68Ni nuclei (i.e. with an isoscalar probe) we developed a CMOS frontend in C35B4C3 AMS technology for the readout of the Double Sided Silicon Strip Detectors acting as ∆E detectors in the FARCOS telescopes. The preamplifier features a continuous-reset feedback and an input PMOS transistor in telescopic cascade configuration. Two options are available for the feedback: an integrated PMOS with aspect ratio suitable to work in the ohmic region and external feedback resistor. The designed input dynamic range is 1.2 GeV. The circuit features a dual polarity input. In order to provide such high dynamic range the feedback resistor – if needed – and capacitor and the compensation capacitor at the gain node are off chip in SMD technology. The GBWP is adequate to prevent shape distortion and the phase margin is greater than 60°. The measured integral-non-linearity keeps below 0.5% up to 1.2 GeV.
The presentation will focus on the design of the charge preamplifier and on the results of the experimental qualification of the circuit standalone and coupled with one strip of the FARCOS Double Sided Silicon Strip Detectors 300 µm and 1500 µm thick.
This work has been supported by INFN in the framework of the NEWCHIM experiment. The help of F. Chiodaroli in the experimental measurements is acknowledged.
Keywords: charge preamplifier, high dynamic range, particle identification, PIGMY resonance