Cold Electronics System Development for ProtoDUNE-SP and SBND LAr TPC (#2533)
F. Liu1, 3, H. Chen1, A. D'Andragora2, J. Fried2, S. Gao1, W. Hou2, S. Li2, V. Radeka2, E. Vernon2, E. Worcester1, M. Worcester1, K. Yethiraj2, B. Yu2
1 Brookhaven National Laboratory, Physics Department, Upton, New York, United States of America
ProtoDUNE-SP and SBND are both liquid argon (LAr) TPCs for neutrino experiments, they share many common development of cold electronics system. Cold electronics decouples the electrode and cryostat design from the readout design. With front-end (FE) electronics integrated with detector electrodes, the noise is independent of the fiducial volume (signal cable lengths), and much lower than with warm electronics. ProtoDUNE-SP cold electronics mainly consist of 960 FE ASICs, 960 ADC ASICs and 120 cold FPGAs to form 120 Front End Mother Board (FEMB) assemblies. Each FEMB assembly is made up of an analog mother board (AM) and an FPGA mezzanine (FM). An AM has 128 channels with 8 FE ASICs and 8 ADC ASICs designed by BNL for 77K-300K operation and long lifetime with low power consumption. The FM multiplexes and transmits 128 channels of data through four 1 Gb/s serial links to the warm interface electronics. SBND cold electronics mainly consist of 120 FEMB assemblies. The SBND design is exploring two different options, the dual gain ADC option and the commercial ADC option. Market survey and cold screening tests for the op-amp and commercial ADC have been performed to evaluate the feasibility of two options. Noise performance of FEMB with 150pF input capacitance has been characterized. ENC is about 1100 electrons at room temperature and about 550 electrons in liquid nitrogen. An integration test stand with 40% APA (Anode Plane Assembly) has been built at BNL, following the DUNE isolation and grounding rules, to further characterize the performance of cold electronics system. The production front-end readout electronics are being fabricated and will be installed in ProtoDUNE-SP in fall 2017, to prepare for the data taking in 2018. SBND front-end readout electronics design will be finalized in 2018, to get ready for the data taking in 2019.
Keywords: Time projection chamber (TPC), Liquid argon TPC, Cold electronics, DUNE, SBND
HLC1: A Front-End ASIC for Liquid Argon Calorimeters (#1809)
G. De Geronimo1, 2, H. Chen3, M. Newcomer4
1 Stony Brook University, Electrical and Computer Engineering, Stony Brook, New York, United States of America
We present a front-end ASIC for liquid argon calorimeters. The preamplifier, of new concept, is based on a fully differential amplifier and it provides at the same time a very low noise programmable termination and single-ended to fully-differential conversion. The preamplifier feeds two fully-differential anti-aliasing bipolar shapers with different gains, designed to achieve an overall dynamic range of 16-bit and characterized by very high drive capability. The ASIC is composed of eight front-end channels, three programmable summing channels relevant for trigger primitives, and a flexible signal generator. Designed and fabricated in a 65nm CMOS technology it is a candidate for the Phase 2 upgrade of the ATLAS LAr Calorimeter.
Keywords: Front-end ASIC, fully differential, low-noise
KLauS4: A mixed signal, low power Silicon Photomultiplier charge readout ASIC (#3286)
K. Briggl1, H. Chen1, Y. Munwes1, D. Schimansky1, H. - C. Schultz-Coulon1, W. Shen1, V. Stankova1, Z. Yuan1
1 Heidelberg University, Kirchhoff Institut fuer Physik, Heidelberg, Baden-Württemberg, Germany
The CALICE collaboration is developing highly granular calorimeter systems for future linear collider experi- ments. The high density of readout channels together with little space for cooling infrastructure limit the power consumption to 25μW per channel, which is achieved by power-pulsing the front-end readout electronics. We present the development of KLauS, a low power mixed mode ASIC for charge readout of Silicon Photomultipliers (SiPMs). Each channel consists of an analog front-end with two charge measurement branches to cover the large dynamic range of the sensors, and a power-efficient ADC with a resolution of 10 bit to digitize the pulse height informations. The quantization resolution can be increased to 12 bit by using an additional pipelined ADC stage. The analog front-end is designed to achieve an excellent signal to noise ratio for single pixel signals using novel low-gain SiPMs, while allowing charge measurements over the full dynamic range of these sensors. Design details of a 7 channel mixed signal prototype ASIC, as well as characterization measurements from laboratory and test-beam set-ups are presented.
Keywords: ASIC, SiPM, CALICE, Low Power, Integrated Readout Electronics
An 8-channel High Dynamic Range ASIC for SiPM-Based Readout of Large Scintillators (#3511)
G. L. Montagnani2, 1, F. Sancandi2, 1, G. Cozzi2, 1, C. Fiorini2, 1, L. Buonanno2, 1, M. Carminati2, 1
1 Politecnico di Milano, Milano, Italy
An 8-channel front-end ASIC was developed in AMS 0.35um CMOS technology to provide a high dynamic range (84 dB) readout of SiPMs coupled to large LaBr3 crystals. The chip exploits a time-variant filtering stage with automatic adjustment of signal-dependent gain across three gains. Every channel provides a low-noise analog output and two digital bits, resulting in a total of 14 bit equivalent dynamic range. The target application is modular multichannel readout suitable, for instance, for large (3”) LaBr3 crystals coupled with 9 arrays of 25 SiPMs (each of area 6 × 6 mm2) to be used for high-resolution gamma spectroscopy in nuclear physics experiments. The high dynamic range is required to cope with the large SiPM signal spread , within an energy range spanning from 100 keV to 20 MeV without requiring manual adjustment the ASIC settings. The experimental characterization of the first 8-channel prototype is reported.
Keywords: SiPM, LaBr3, Scintillator, Frontend
Characterizatin results for PLATO: a prototype CMOS readout chip for hybrid X-ray photon counting detectors with low thresholds for fusion plasma diagnostics (#2039)
A. Habib1, M. Menouni1, D. Fougeron1, P. Pangaud1, C. Fenzi2, G. Colledani2, G. Moureau2, A. Escarguel3, C. Morel1
1 Aix-Marseille Université, CNRS/IN2P3, CPPM, Marseille, France
PLATO is a prototype readout chip developed in CMOS 130 nm technology for hybrid photon counting detectors. The chip is designed to meet specifications for fusion plasma diagnostics in the WEST Tokamak of CEA-Cadarache, with potential perspectives for ITER. The main challenge is to achieve a sufficiently low detection threshold, in order to detect X-ray plasma fluorescence at energies between 3 keV and 8 keV. The prototype chip is a 16 × 18 pixel matrix with a 70 µm pixel pitch. Each pixel contains a charge sensitive amplifier, two discriminators and two 12-bit counters. Novel techniques are used to reduce coupling noise between pixels and to minimize threshold dispersion across the matrix. First characterization results show an equivalent noise charge of 45 e--rms, a conversion gain of 69 mV/ke- with a non-linearity less than 5%. The design is optimized for low power consumption of 5.2 µW per pixel.
Keywords: CMOS pixel, photon counting, readout chip, X-ray imaging, fusion plasma diagnostics, Analog front end electronics
Low-noise and low-power binary front-end in 130nm CMOS for triple-GEM detectors supporting wide range of detector capacitances with gain and peaking time programmability. (#2507)
M. Dabrowski1, 2, P. Aspell2, G. De Lentdecker5, G. De Robertis3, A. Irschad2, F. Licciulli3, F. Loddo3, H. Petrow4, J. Rosa5, T. Tuuva4, F. Tavernier1, P. Leroux1
1 KU Leuven, Leuven, Belgium
Analog front-end in 130nm CMOS technology was developed for the readout of triple-GEM detectors in the CMS experiment at CERN. The front-end is highly programmable by means of the peaking time (25ns, 50ns, 75ns and 100ns) and the maximum signal range (13fC, 40fC and 75fC) and is able to support a detector capacitance of 1pF to 100pF. In the design, many optimization techniques have been used to minimize the power consumption for given noise and timing specifications. Consequently, the preamplifier, the shaper and the single-to-differential amplifier consume 850uA of current per channel having the equivalent noise charge (ENC) below 1260e- for 20pF detector capacitance and the noise slope of 40e-/pF. For the ease of peaking time programmability, an OTA-C based shaper was employed. The discriminator is implemented as Constant-Fraction Discriminator (CFD), it consumes additional 300uA of current and allows reduction of the time-walk to less than one nanosecond. The entire design has been made radiation hard against TID. A chip comprising 128 front-end channels was fabricated and tested.
Keywords: low-noise, low-power, radiation tolerant, triple-GEM, OTA-C shaper, front-end for gem, pre-amplifier, compact muon solenoid, detectors