IEEE 2017 NSS/MIC/RTSD ControlCenter

Online Program Overview Session: N-05

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Analog and Digital Circuits I

Session chair: Farah Fahim FERMILab; Shaorui Li BNL, Instrumentation Division, Upton (USA)
 
Shortcut: N-05
Date: Monday, October 23, 2017, 16:00
Room: Centennial II
Session type: NSS Session

Contents

4:00 pm N-05-1 Download

Test results of the CHIPIX65 asynchronous front-end for the HL-LHC experiment upgrades (#3232)

L. Gaioni1, 2, F. De Canio1, M. Manghisoni1, 2, L. Ratti1, 3, V. Re1, 2, G. Traversi1, 2

1 INFN, Pavia, Pavia, Italy
2 University of Bergamo, Dept. of Engineering and Applied Sciences, Bergamo, Italy
3 University of Pavia, Dept. of Electrical, Computer and Biomedical Engineering, Pavia, Italy

Content

This work is concerned with the design and the experimental characterization of an analog front-end processor conceived for experiments with unprecedented particle rates and radiation levels at the High-Luminosity LHC (HL-LHC). The front-end channel discussed in this paper is part of the CHIPIX65-FE0 prototype, a readout ASIC designed in a 65 nm CMOS technology in the framework of the RD53 collaboration. The prototype integrates a 64x64 matrix with 50 um pitch, featuring two different analog front-end architectures working in parallel (two 32x64 sub-matrices), one with asynchronous and one with synchronous hit discriminator. The paper will be focused on the characterization of the array with asynchronous channels, featuring a charge sensitive amplifier with Krummenacher feedback and a fast threshold discriminator exploited for time-over-threshold (ToT) analog-to-digital conversion. The analog front-end circuit takes an overall area not exceeding 35 um x 35 um, with a power dissipation per channel close to 5 uW. The mean equivalent noise charge is 90 electrons (with no sensor connected to the front-end) with a tuned threshold dispersion close to 45 electrons, which, together, guarantee very low (smaller than 1000 electrons) stable threshold operation.

Keywords: Pixel detectors, Analog Front-end, CMOS, High-Luminosity LHC
4:18 pm N-05-2 Download

Design and Performance of the SALT ASIC for the LHCb Upstream Tracker Upgrade (#2240)

T. Fiutowski1

1 AGH University of Science and Technology, Faculty of Physics and Applied Computer Science, Krakow, Poland

On behalf of the LHCb UT Working Group

Content

The performance of present Large Hadron Collider beauty (LHCb) detector is limited by readout electronics and data acquisition architecture. After the upgrade of LHC machine it will be capable to deliver more than one order of magnitude higher luminosity than presently used. To achieve this goal various sub-detectors will need a new faster front-end electronics with the readout running at the bunch-crossing rate of 40 MHz.

The SALT is a 128-channel readout ASIC designed for the LHCb Upstream Tracker. It will extract and digitize analog signals from the silicon microstrip sensor, perform digital processing and transmit serial output data. It is designed in CMOS 130 nm process and uses a novel architecture comprising an analog front-end with fast baseline restoration and an ultra-low power (< 0.5 mW) fast sampling (40 MSps) 6-bit ADC in each channel.

Prototypes of all important SALT blocks, i.e. 8-channel analogue front-end, 8-channel 6-bit ADC, PLL, DLL and, SLVS I/O were designed, fabricated and tested, showing very good performance.  An 8-channel SALT prototype comprising all important functionalities was produced and found, in tests, to be fully functional. The first 128-channel version of ASIC was also produced and thoroughly tested.  In this paper studies on the first prototype of the full chip will be presented as well as the optimized design.

Keywords: Front-end electronics for detector readout, VLSI circuits, Digital signal processing (DSP)
4:36 pm N-05-3

Design and performance of the TIGER front-end ASIC for the BESIII Cylindrical Gas Electron Multiplier detector (#1807)

F. Cossio1, 2, M. Alexeev2, 3, R. Bugalho5, J. Chai1, 4, M. D. Da Rocha Rolo2, A. Di Francesco6, M. Greco2, 3, H. Li4, 2, M. Maggiora2, 3, S. Marcello2, 3, M. Mignone2, A. Rivetti2, J. Varela6, 5, R. Wheadon2

1 Politecnico di Torino, Torino, Italy
2 Istituto Nazionale di Fisica Nucleare, sez. di Torino, Torino, Italy
3 Università di Torino, Dipartimento di Fisica, Torino, Italy
4 Institute of High Energy Physics, Beijing, China
5 PETsys Electronics, Oeiras, Portugal
6 LIP, Lisbon, Portugal

Content

We present the design and characterization of the TIGER (Turin Integrated Gem Electronics for Readout) front-end ASIC, developed for the readout of signals coming from the CGEM (Cylindrical Gas Electron Multiplier) detector, the new inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The detector is scheduled to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM with about 10.000 channels, which are readout by 160 dedicated front-end TIGER ASICs. To achieve the required spatial resolution of the order of 100 µm an analog readout with charge interpolation has been chosen.

Each ASIC includes 64 channels, references and bias generators, an internal test pulse calibration circuitry and a digital global controller. The design features a charge sensitive amplifier coupled to a dual-branch shaper stage, optimized for timing and charge measurement, followed by a mixed-mode back-end that extracts and digitizes the timestamp and charge of the input signal. The time-of-arrival is provided by a set of low-power TDCs, based on analog interpolation techniques, while the charge measurement is obtained either from the time-over-threshold information or the 10-bit digitization of the signal peak amplitude, which is provided by a sample-and-hold circuit operated as digitally-controlled peak detector. The flexibility of this multiple readout scheme, together with the possibility to operate the CGEM as a micro Time Projection Chamber, allows to maximize the CGEM spatial resolution within the large BESIII magnetic field.

The ASIC has been fabricated in a 110 nm CMOS technology and designed to operate with a 1.2 V power supply, an input capacitance of about 100 pF, an input dynamic range between 1 and 50 fC, a power consumption of 10 mW/channel and a sustained event rate of 60 kHz/channel. The design and test results of TIGER first prototype are presented showing its full functionality.

Keywords: front-end ASIC, mixed-signal design, ASIC characterization, BESIII, GEM
4:54 pm N-05-4 Download

Experimental characterization of the TOFPET2 Rev-b ASIC (#2174)

R. Bugalho2, A. Di Francesco1, L. Ferramacho2, C. Leong2, T. Niknejad1, M. Rolo3, J. C. Silva1, 2, R. Silva1, 2, M. Silveira2, S. Tavernier2, 4, J. Varela1, 2

1 LIP, Lisbon, Lisbon, Portugal
2 PETsys Electronics, Porto Salvo, Portugal
3 INFN, Torino, Torino, Italy
4 Vrije Universiteit, Brussel, Ixelles, Belgium

Content

We present the recent experimental characterization of the TOFPET2 Rev-b, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit is designed in CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration ADCs in each channel. The Coincidence Time Resolution (CTR) of 511 keV photon pairs from 22Na point source measured with 3x3x5 mm3 LYSO crystals and 4x4mm2 SiPMs is of 164 ps FWHM. The energy resolution achieved for the 511keV peak is 10.5% FWHM.

Keywords: ASIC, TOFPET, SiPM, PET, LYSO, Time-of-Flight
5:12 pm N-05-5

TERA: A Readout IC for Ultra High Rate X-ray Detection Applications (#2249)

G. Bellotti1, 2, I. Hafizh1, 2, M. Carminati1, 2, C. E. Fiorini1, 2

1 Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Milano, Italy
2 INFN, Sezione di Milano, Milano, Italy

Content

This work presents TERA (Throughput Enhanced Readout ASIC), a multichannel low-noise readout ASIC designed for ultra-high-rate x-ray detection applications. The chip has been developed to process signals coming from Silicon Drift Detectors (SDDs) coupled to Charge Sensitive Amplifiers (CSA), such as CUBE, with enhanced high throughput capability and good noise performance. The first prototype here presented is composed of 4 parallel readout channels, each one including a 7th order semi-Gaussian shaping-amplifier. The filter has been chosen to minimize series noise, ballistic deficit, and pile-up effect. The channel is able to accommodate four different energy ranges: 5, 10, 20, and 30 keV, and four different filter shaping times: 200, 400, 1000, and 2000 ns (pulse width at 1% of the peak amplitude). The output of the shaper is followed by a peak stretcher and an analog memory. The analog memory serves as a buffer to temporarily store the peak values, thus increasing the throughput in Poisson-distributed events with average count rate comparable to the acquisition readout frequency. An independent peak detector circuit and a novel pile-up-rejector strategy have been also developed to maximize the throughput. Readout channels are organized in 2 independent subsets of 2 channels, each one read sequentially, buffered by single-ended to differential op amp, and digitized by a successive-approximation-register (SAR) 12-bit ADC, providing the maximum sampling rate for each channel of 2 Mcps. The simulations suggest that in the case of Poisson-distributed events with the average input count rate of 3 Mcps, the channel throughput can reach up to 1.75 Mcps.

Keywords: SDD, Spectroscopy, High-speed, analog electronics, mixed signals elecronics, ASIC, multichannel, low noise
5:30 pm N-05-6

ASoC: A High Performance Waveform Sampling and Feature Extraction System-on-Chip for Data Acquisition (#2270)

I. Mostafanezhad1, L. Macchiarulo1, B. Edralin2, G. Varner2

1 Nalu Scientific, LLC, Honolulu, Hawaii, United States of America
2 University of Hawaii, Physics, Honolulu, Hawaii, United States of America

Content

Readout electronics for modern particle imaging based identification detectors must be compact, low power, deliver acceptable timing resolution and be robust to pile-ups. The solution is to integrate full waveform sampling, analog buffering and feature extraction and digital signal processing into one single Application Specific Integrated Circuit (ASoC in the following). ASoC can be used as a building block for such readout devices. The prototype ASoC has 4 channels, operates at 3 GSa/s and has on-chip trigger timestamping, calibration and signal processing capabilities. ASoC also provides 8k storage samples per channel which makes it  suitable for large experiments.

Keywords: Waveform Sampling, Analog to digital converter, System-on-Chip, Low Cost, Low power